Agilent’s Transactional decoder includes a transactional viewer that allows the designer to select transactional queues and performance information from the analyzer’s NVMe transaction overview pane.

Ключевые возможности и технические характеристики

PCI express generation 1, 2, & 3 protocol architecture

  • Lane speeds 2.5 GT/s, 5.0 GT/s, and 8.0 GT/s
  • Lane widths x1, x4, x8, and x16
  • Stimulus response testing with the addition of the U4305A protocol exerciser

NVMe device analysis and emulation

  • Compact AXIe modular system configuration

Описание

Agilent’s Transactional decoder includes a transactional viewer that allows the designer to select transactional queues and performance information from the analyzer’s NVMe transaction overview pane. This organizes the transactions by direction or by queue to follow the data flow across the interface, with one-click control. Individual PRP (Physical Region Page) lists contain all of the key information of the NVMe queues, allowing designers to quickly review and validate the data flows over the PCIe connections.

 

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